As integrated circuitry continues to shrink in size, efforts are ongoing to find novel methods of forming integrated circuitry structures and related integrated circuitry which improve upon those methods currently utilized and the resultant structures formed thereby. One type of integrated circuitry is memory circuitry and arrays. Such circuitry has been and continues to be the focus of intense efforts to reduce the size of the circuitry, increase the speed with which such circuitry operates, and maintain or increase the ability of such circuitry to perform its memory function. The industry designers continually search for ways to reduce the size of memory circuitry without sacrificing array performance.
One such way is by improving on the design of transistor structures which are incorporated into memory circuitry. Transistor structures or devices have numerous applications for semiconductor circuitry. For instance, transistor structures can be incorporated into memory circuitry (such as, for example, dynamic random access memory (DRAM)) and logic circuitry. DRAM circuitry usually includes an array of memory cells interconnected by rows and columns, which are known as word lines and digit lines (or bit lines), respectively. A typical DRAM memory cell comprises a transistor structure connected with a charge storage device or data storage element (such as, for example, a capacitor device).
Typical transistor structures comprise a channel region between a pair of source/drain regions, and a gate configured to electrically connect the source/drain regions to one another through the channel region. The transistor constructions utilized in semiconductor constructions will be supported by a semiconductor substrate. The semiconductor substrate will have a primary surface which can be considered to define a horizontal direction or horizontal surface. Transistor devices can be divided amongst two broad categories based upon the orientations of the channel regions relative to the primary surface of the semiconductor substrate. Specifically, transistor structures which have channel regions that are primarily parallel to the primary surface of the substrate are referred to as planar transistor structures, and those having channel regions which are generally perpendicular to the primary surface of the substrate are referred to as vertical transistor structures. Since current flow between the source and drain regions of a transistor device occurs through the channel region, planar transistor devices can be distinguished from vertical transistor devices based upon the direction of current flow as well as on the general orientation of the channel region. Specifically, vertical transistor devices are devices in which the current flow between the source and drain regions of the devices is primarily substantially orthogonal to a primary surface of a semiconductor substrate, and planar transistor devices are devices in which the current flow between source and drain regions is primarily parallel to the primary surface of the semiconductor substrate.
There is a continuing interest in the development of methodologies by which vertical transistor devices can be incorporated into integrated circuitry applications due to, among other things, advantages in packing density that can be obtained utilizing vertical transistor devices relative to planar transistor devices. Difficulties are frequently encountered in attempting to produce the vast arrays of vertical transistor devices desired for semiconductor applications while maintaining suitable performance characteristics of the devices. For example, present methodologies for forming vertical transistor devices include forming or growing epitaxial silicon posts or pillars to extend upward from the primary or horizontal surface of the semiconductor substrate. The epitaxial silicon posts or pillars are used as the transistor channels in present designs of vertical transistor devices. However, this design creates several problems. For example, a high defect density has resulted with potential cell leakage issues. Additionally, the design promotes a floating body effect in the transistor channel which complicates and increases the difficulty of controlling the gate threshold voltage of the transistor. Accordingly, it is desired to develop new methods for fabricating vertical transistor devices that improve upon and/or at least diminish or alleviate these problems.